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lc 2 mos complete, 12-bit, 100 khz, sampling adcs ad7870/ad7875/ad7876 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1997C2009 analog devices, inc. all rights reserved. features complete monolithic 12-bit adcs with 2 s track-and-hold amplifier 8 s adc on-chip reference laser-trimmed clock parallel, byte, and serial digital interface 72 db snr at 10 khz input frequency (ad7870, ad7875) 57 ns data access time low power: ?60 mw typical variety of input ranges 3 v for ad7870 0 v to +5 v for ad7875 10 v for ad7876 functional block diagram ref out v in input scaling 12-bit dac parallel and serial interface ad7870/ad7875/ ad7876 control logic clock 3v reference sar + counter comp track-and-hold v dd v ss dgnd 07730-001 db11 db0 cs rd busy/int agnd clk convst 12/8/clk figure 1. general description the ad7870/ad7875/ad7876 are fast, complete, 12-bit analog-to-digital converters (adcs). these converters consist of a track-and-hold amplifier, an 8 s successive approximation adc, a 3 v buried zener reference, and versatile interface logic. the adcs feature a self-contained internal clock which is laser trimmed to guarantee accurate control of conversion time. no external clock timing components are required; the on-chip clock may be overridden by an external clock if required. the parts offer a choice of three data output formats: a single, parallel, 12-bit word; two 8-bit bytes or serial data. fast bus access times and standard control inputs ensure easy interfacing to modern microprocessors and digital signal processors. all parts operate from 5 v power supplies. the ad7870 and ad7876 accept input signal ranges of 3 v and 10 v, respec- tively, while the ad7875 accepts a unipolar 0 v to +5 v input range. the parts can convert full power signals up to 50 khz. the ad7870/ad7875/ad7876 feature dc accuracy specifica- tions, such as linearity, full-scale and offset error. in addition, the ad7870 and ad7875 are fully specified for dynamic performance parameters including distortion and signal-to- noise ratio. the parts are available in a 24-pin, 0.3 inch-wide, plastic or hermetic dual-in-line package (dip). the ad7870 and ad7875 are available in a 28-pin plastic leaded chip carrier (plcc), while the ad7876 is available and in a 24-pin small outline (soic) package. product highlights 1. complete 12-bit adc on a chip. the ad7870/ad7875/ad7876 provide all the functions necessary for analog-to-digital conversion and combine a 12-bit adc with internal clock, track-and-hold amplifier and reference on a single chip. 2. dynamic specifications for dsp users. the ad7870 and ad7875 are fully specified and tested for ac parameters, including signal-to-noise ratio, harmonic distortion and intermodulation distortion. 3. fast microprocessor interface. data access times of 57 ns make the parts compatible with modern 8-bit and 16-bit microprocessors and digital signal processors. key digital timing parameters are tested and guaranteed over the full operating temperature range.
ad7870/ad7875/ad7876 rev. c | page 2 of 2 8 table of contents features .............................................................................................. 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ad7870 specifications ................................................................. 3 ? ad7875/ad7876 specifications ................................................. 4 ? timing characteristics ................................................................ 6 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configurations and function descriptions ........................... 8 ? load circuits ................................................................................... 10 ? converter details ............................................................................ 11 ? internal reference ...................................................................... 11 ? track-and-hold amplifier ........................................................ 11 ? analog input ............................................................................... 11 ? offset and full-scale adjustmentad7870 ........................ 12 ? offset and full-scale adjustmentad7876 ........................ 13 ? offset and full-scale adjustmentad7875 ........................ 13 ? timing and control ....................................................................... 14 ? data output formats ................................................................. 14 ? mode 1 interface ......................................................................... 14 ? mode 2 interface ......................................................................... 15 ? dynamic specifications ............................................................. 16 ? microprocessor interface ............................................................... 19 ? parallel read interfacing ........................................................... 19 ? two-byte read interfacing ....................................................... 19 ? serial interfacing ........................................................................ 20 ? standalone operation ................................................................ 21 ? applications information .............................................................. 22 ? layout hints ................................................................................ 22 ? noise ............................................................................................ 22 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 25 ? revision history 2/09rev. b to rev. c updated format .................................................................. universal reorganized layout ............................................................ universal deleted s version ................................................................ universal changes to internal clock parameter, table 1 and added endnote to table 1 ............................................................... 4 changes to internal clock parameter, table 2 .............................. 5 changes to mode 1 interface section .......................................... 14 deleted data acquisition board and interface connections sections and figure 26 ................................................................... 15 deleted figure 27 and power supply connections, shorting plug options and components list sections ............................. 16 deleted figure 28 and figure 29 ................................................... 17 deleted figure 30 and figure 31 ................................................... 18 updated outline dimensions ....................................................... 23 changes to ordering guide .......................................................... 25
ad7870/ad7875/ad7876 rev. c | page 3 of 28 specifications v dd = +5 v 5%, v ss = ?5 v 5%, agnd = dgnd = 0 v, f clk = 2.5 mhz external, unless otherwise stated. all specifications t min to t max , unless otherwise noted. ad7870 specifications table 1. adn7870 1 parameter j, a k, b l, c t units test conditions/comments dynamic performance 2 signal-to-noise ratio 3 (snr) @ +25c 70 70 72 69 db min v in = 10 khz sine wave, f sample = 100 khz t min to t max 70 70 71 69 db min typically 71.5 db for 0 < v in < 50 khz total harmonic distortion (thd) ?80 ?80 ?80 ?78 db max v in = 10 khz sine wave, f sample = 100 khz typically ?86 db for 0 < v in < 50 khz peak harmonic or spurious noise ?80 ?80 ?80 ?78 db max v in = 10 khz, f sample = 100 khz typically ?86 db for 0 < v in < 50 khz intermodulation distortion (imd) second order terms ?80 ?80 ?80 ?78 db max fa = 9 khz, fb = 9.5 khz, f sample = 50 khz third order terms ?80 ?80 ?80 ?78 db max fa = 9 khz, fb = 9.5 khz, f sample = 50 khz track-and-hold acquisition time 2 2 2 2 s max dc accuracy resolution 12 12 12 12 bits minimum resolution for which no missing codes are guaranteed 12 12 12 12 bits integral nonlinearity 1/2 1/2 1/4 1/2 lsb typ integral nonlinearity 1 1/2 1 lsb max differential nonlinearity 1 1 1 lsb max bipolar zero error 5 5 5 5 lsb max positive full-scale error 4 5 5 5 5 lsb max negative full-scale error 4 5 5 5 5 lsb max analog input input voltage range 3 3 3 3 v input current 500 500 500 500 a max reference output ref out @ +25c 2.99 2.99 2.99 2.99 v min 3.01 3.01 3.01 3.01 v max ref out tempco 60 60 35 35 ppm/c max reference load sensitivity (ref out/i) 1 1 1 1 mv max reference load current change (0 a to 500 a). reference load should not be changed during conversion. logic inputs input high voltage, v inh 2.4 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 10 a max v in = 0 v to v dd input current (12/ 8 /clk input only) 10 10 10 10 a max v in = v ss to v dd input capacitance, c in 5 10 10 10 10 pf max logic outputs output high voltage, v oh 4.0 4.0 4.0 4.0 v min i source = 40 a output low voltage, v ol 0.4 0.4 0.4 0.4 v max i sink = 1.6 ma db11 to db0 floating-state leakage current 10 10 10 10 a max floating-state output capacitance 5 15 15 15 15 pf max
ad7870/ad7875/ad7876 rev. c | page 4 of 28 adn7870 1 parameter j, a k, b l, c t units test conditions/comments conversion time external clock (f clk = 2.5 mhz) 8 8 8 8 s max internal clock 6 6.5/9 6.5/9 6.5/9 6.5/9 s min/ s max power requirements v dd +5 +5 +5 +5 v nom 5% for specified performance v ss ?5 ?5 ?5 ?5 v nom 5% for specified performance i dd 13 13 13 13 ma max typically 8 ma i ss 6 6 6 6 ma max typically 4 ma power dissipation 95 95 95 95 mw max typically 60 mw 1 the temperature range for the j, k, and l versions is from 0c to +70c; for the a, b, and c versions is?40c to +85c; and f or the t version is ?55c to +125c. 2 v in (p-p) = 3 v. 3 snr calculation includes dist ortion and noise components. 4 measured with respect to internal refere nce and includes bipolar offset error. 5 sample tested @ +25c to ensure compliance. 6 conversion time specification for the ad7870a device with inte rnal clock used is 8 s/10 s minimum/maximum. ad7875/ad7876 specifications table 2. parameter ad7875/ad7876 1 units test conditions/comments k, b l, c t dc accuracy resolution 12 12 12 bits min resolution for which no missing codes are guaranteed 12 12 12 bits integral nonlinearity @ +25c 1 1/2 1 lsb max t min to t max (ad7875 only) 1 1 1 lsb max t min to t max (ad7876 only) 1 1/2 1 lsb max differential nonlinearity 1 1 1.5/?1.0 lsb max unipolar offset error (ad7875 only) 5 5 5 lsb max bipolar zero error (ad7876 only) 6 2 6 lsb max full-scale error at +25c 2 8 8 8 lsb max typical full-scale error is 1 lsb full-scale tc 2 60 35 60 ppm/c max typical tc is 20 ppm/c track-and-hold acquisition time 2 2 2 s max dynamic performance 3 (ad7875 only) signal-to-noise ratio 4 (snr) @ +25c 70 72 69 db min v in = 10 khz sine wave, f sample = 100 khz t min to t max 70 71 69 db min typically 71.5 db for 0 < v in < 50 khz total harmonic distortion (thd) ?80 ?80 ?78 db max v in = 10 khz sine wave, f sample = 100 khz typically ?86 db for 0 < v in < 50 khz peak harmonic or spurious nois e ?80 ?80 ?78 db max v in = 10 khz, f sample = 100 khz typically ?86 db for 0 < v in < 50 khz intermodulation distortion (imd) second order terms ?80 ?80 ?78 db max fa = 9 khz, fb = 9.5 khz, f sample = 50 khz third order terms ?80 ?80 ?78 db max fa = 9 khz, fb = 9.5 khz, f sample = 50 khz
ad7870/ad7875/ad7876 rev. c | page 5 of 28 parameter ad7875/ad7876 1 units test conditions/comments k, b l, c t analog input ad7875 input voltage range 0 to +5 0 to +5 0 to +5 v ad7875 input current 500 500 500 a max ad7876 input voltage range 10 10 10 v ad7876 input current 600 600 600 a max reference output ref out @ +25c 2.99 2.99 2.99 v min 3.01 3.01 3.01 v max ref out tempco 60 35 60 ppm/c max typical tempco is 20 ppm/c reference load sensitivity (ref out/i) ?1 ?1 ?1 mv max reference load current change (0 a to 500 a). reference load should not be changed during conversion. logic inputs input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 a max v in = 0 v to v dd input current (12/ 8 /clk input only) 10 10 10 a max v in = v ss to v dd input capacitance, c in 5 10 10 10 pf max logic outputs output high voltage, v oh 4.0 4.0 4.0 v min i source = 40 ma output low voltage, v ol 0.4 0.4 0.4 v max i sink = 1.6 ma db11Cdb0 floating-state leakage current 10 10 10 a max floating-state output capacitance 5 15 15 15 pf max conversion time external clock (f clk = 2.5 mhz) 8 8 8 s max internal clock 6.5/9 6.5/9 6.5/9 s min/s max power requirements as per ad7870 refer to the power requirements in table 1 . 1 for the ad7875, the temperature range for the k and l versions is from 0c to +70c; for the b and c versions is?40c to +85c ; and for the t version is ?55c to +125c. for the ad7876, the temperature range for the b and c versions is from ?40c to +85c and for the t version is?55c to +125c. 2 includes internal reference error and is calculated after unipolar offset er ror (ad7875) or bipolar zero error (ad7876) has be en adjusted out. full-scale error refers to both positive and negative fu ll-scale error for the ad7876. 3 dynamic performance parameters are no t tested on the ad7876, but these are typically the same as for the ad7875. 4 snr calculation includes dist ortion and noise components. 5 sample tested @ +25c to ensure compliance.
ad7870/ad7875/ad7876 rev. c | page 6 of 28 timing characteristics v dd = +5 v 5%, v ss = ?5 v 5%, agnd = dgnd = 0 v. see figure 14 , figure 15 , figure 16 , and figure 17 . timing specifications are sample tested at 25c to ensure compliance, unless otherwise noted. all input signals are specified with t r = t f = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. table 3. parameter 1 limit at t min , t max (j, k, l, a, b, c versions) limit at t min , t max (t version) units conditions/comments t 1 50 50 ns min convst pulse width t 2 0 0 ns min cs to rd setup time (mode 1) t 3 2 60 75 ns min rd pulse width t 4 0 0 ns min cs to rd hold time (mode 1) t 5 70 70 ns max rd to int delay t 6 2 , 3 57 70 ns max data access time after rd t 7 2 , 4 5 5 ns min bus relinquish time after rd 50 50 ns max t 8 0 0 ns min hben to rd setup time t 9 0 0 ns min hben to rd hold time t 10 100 100 ns min sstrb to sclk falling edge setup time t 11 5 370 370 ns min sclk cycle time t 12 6 135 150 ns max sclk to valid data delay. c l = 35 pf t 13 20 20 ns min sclk rising edge to sstrb 100 100 ns max t 14 10 10 ns min bus relinquish time after sclk 100 100 ns max t 15 60 60 ns min cs to rd setup time (mode 2) t 16 120 120 ns max cs to busy propagation delay t 17 200 200 ns min data setup time prior to busy t 18 0 0 ns min cs to rd hold time (mode 2) t 19 0 0 ns min hben to cs setup time t 20 0 0 ns min hben to cs hold time 1 serial timing is measured with a 4.7 k pull-up resistor on sdata and sstrb and a 2 k pull-up on sclk. the capacitance on all three outputs is 35 pf. 2 timing specifications for t 3 , t 6 , and for the maximum limit at t 7 are 100% production tested. 3 t 6 is measured with the load circ uits of figure 4 and defined as the time required for an output to cross 0.8 v or 2.4 v. 4 t 7 is defined as the time required for the data lines to change 0.5 v when loaded with the circuits of figure 5. 5 sclk mark/space ratio (measured from a vo ltage level of 1.6 v) is 40/60 to 60/40. 6 sdata will drive higher capacitive loads but this will add to t 12 since it increases the external rc time constant (4.7 k||c l ) and thus the time to reach 2.4 v.
ad7870/ad7875/ad7876 rev. c | page 7 of 28 absolute maximum ratings table 4. parameter rating v dd to agnd ?0.3 v to +7 v v ss to agnd +0.3 v to ?7 v agnd to dgnd ?0.3 v to v dd +0.3 v v in to agnd ?15 v to +15 v ref out to agnd 0 v to v dd digital inputs to dgnd ?0.3 v to v dd +0.3 v digital outputs to dgnd ?0.3 v to v dd +0.3 v operating temperature range commercial (j, k, l versionsCad7870) 0c to +70c commercial (k, l versionsCad7875) 0c to +70c industrial (a, b, c versionsCad7870) ?25c to +85c industrial (b, c versionsCad7875/ ad7876) ?40c to +85c extended (t version) ?55c to +125c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) +300c power dissipation (any package) to +75c 450 mw derates above +75c by 10 mw/c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7870/ad7875/ad7876 rev. c | page 8 of 2 8 pin configurations and function descriptions rd 1 busy/int 2 clk 3 db11/hben 4 cs 24 convst 23 12/8/clk 22 v ss 21 db10/sstrb 5 db9/sclk 6 db8/sdata 7 v in 20 ref out 19 agnd 18 db7/low 8 v dd 17 db6/low 9 db0/db8 16 db5/low 10 db1/db9 15 db4/low 11 db2/db10 14 dgnd 12 db3/db11 13 ad7870/ ad7875/ ad7876 top view (not to scale) 07730-004 figure 2. dip and soic pin configuration 1282726 234 5 6 7 8 9 10 11 25 24 23 22 21 20 19 nc = no connect db11/hben db10/sstrb db9/sclk nc db8/sdata db7/low db6/low v ss v in ref out nc agnd v dd db0/db8 clk busy/int rd nc cs convst 12/8/clk db5/low db4/low dgnd nc db3/db11 db2/db10 db1/db9 pin 1 indentfier 12 13 14 15 16 17 18 07730-005 ad7870/ad7875/ ad7876 top view (not to scale) figure 3. plcc pin configuration table 5. pin function descriptions dip and soic pin no. plcc pin no. mnemonic function n/a 1, 8, 15, 22 nc no connect. 1 2 rd read. active low logic input. this input is used in conjunction with cs low to enable the data outputs. 2 3 busy / int busy/interrupt. active low logic output indicating converter status. see figure 14, figure 15, figure 16 , and figure 17. 3 4 clk clock input. an external ttl-compatible clock may be applied to this input pi n. alternatively, tying this pin to v ss enables the internal laser-trimmed clock oscillator. 4 5 db11/hben data bit 11 (msb)/high byte enable. the function of this pin is dependent on the state of the 12/ 8 /clk input. when 12-bit parallel data is selected, this pin provides the db11 output. when byte data is selected, this pin becomes the hben logic input. hben is used for 8-bit bus interfacing. when hben is low, db7/low to db0/db8 become db7 to db0. with hben high, db7/low to db0/db8 are used for the upper byte of data (see ). table 6 5 6 db10/ sstrb data bit 10/serial strobe. when 12-bit parallel da ta is selected, this pin provides the db10 output. sstrb is an active low open-drain output that provides a strobe or framing pulse for serial data. an external 4.7 k pull-up resistor is required on sstrb . 6 7 db9/sclk data bit 9/serial clock. when 12-bit parallel data is selected, th is pin provides the db9 output. sclk is the gated serial clock output derived from the internal or external adc clock. if the 12/ 8 /clk input is at ?5 v, then sclk runs continuously. if 12/ 8 /clk is at 0 v, then sclk is gated off after serial transmission is complete. sclk is an open-drain output and re quires an external 2 k pull-up resistor. 7 9 db8/sdata data bit 8/se rial data. when 12-bit parallel data is select ed, this pin provides the db8 output. sdata is an open-drain serial data output which is used with sclk and sstrb for serial data transfer. serial data is valid on the falling edge of sclk while sstrb is low. an external 4.7 k pull-up resistor is required on sdata. 8 to11 10 to 13 db7/lowC db4/low three-state data outputs controlled by cs and rd . their function depends on the 12/ 8 /clk and hben inputs. with 12/ 8 /clk high, they are always db7Cdb4. with 12/ 8 /clk low or ?5 v, their function is controlled by hben (see ). table 6 12 14 dgnd digital ground. ground reference for digital circuitry. 13 to 16 16 to 19 db3/db11C db0/db8 three-state data outputs which are controlled by cs and rd . their function depends on the 12/ 8 /clk and hben inputs. with 12/ 8 /clk high, they are always db3Cdb0. with 12/ 8 /clk low or ?5 v, their function is controlled by hben (see ). table 6 17 20 v dd positive supply, +5 v 5%.
ad7870/ad7875/ad7876 rev. c | page 9 of 28 dip and soic pin no. plcc pin no. mnemonic function 18 21 agnd analog ground. ground refere nce for track-and-hold, reference and dac. 19 23 ref out voltage reference output. the internal 3 v referenc e is provided at this pin. the external load capability is 500 a. 20 24 v in analog input. the analog input range is 3 v for th e ad7870, 10 v for the ad7876, and 0 v to +5 v for the ad7875. 21 25 v ss negative supply, ?5 v 5%. 22 26 12/ 8 /clk three function input. defines the data format and seri al clock format. with this pin at +5 v, the output data for-mat is 12-bit parallel only. with this pin at 0 v, either byte or serial data is available and sclk is not continuous. with this pin at ?5 v, either byte or serial data is again available but sclk is now continuous. 23 27 convst convert start. a low to high transition on this input puts the track-and-hold into its hold mode and starts conversion. this input is asynchronous to the clk input. 24 28 cs chip select. active low logic input. the device is selected when this input is active. with convst tied low, a new conversion is initiated when cs goes low. table 6. output data for byte interfacing hben db7/low db6/low db5/low db4/lo w db3/db11 db2/db10 db1/db9 db0/db8 high low low low low db11(msb) db10 db9 db8 low db7 db6 db5 db4 db3 db2 db1 db0 (lsb)
ad7870/ad7875/ad7876 rev. c | page 10 of 28 load circuits 07730-003 3k? dgnd dbn 10pf 3k? 5 v dgnd v oh to high-z v ol to high-z dbn 10pf 07730-002 56k? dgnd dbn 50pf 56k? dgnd high-z to v oh high-z to v ol dbn 50pf 5 v figure 5. load circuits for output float delay figure 4. load circuits for access time
ad7870/ad7875/ad7876 rev. c | page 11 of 28 converter details the ad7870/ad7875/ad7876 is a complete 12-bit adc, requiring no external components apart from power supply decoupling capacitors. it is comprised of a 12-bit successive approximation adc based on a fast settling voltage output dac, a high speed comparator and sar, a track-and-hold amplifier, a 3 v buried zener reference, a clock oscillator, and control logic. internal reference the ad7870/ad7875/ad7876 have on-chip temperature compensated buried zener reference that is factory trimmed to 3 v 10 mv. internally it provides both the dac reference and the dc bias required for bipolar operation (ad7870 and ad7876). the reference output is available (ref out) and capable of providing up to 500 a to an external load. the maximum recommended capacitance on ref out for normal operation is 50 pf. if the reference is required for use external to the adc, it should be decoupled with a 200 resistor in series with a parallel combination of a 10 f tantalum capacitor and a 0.1 f ceramic capacitor. these decoupling components are required to remove voltage spikes caused by the adcs internal operation. temperature compensation ad7870/ad7875/ad7876 ref out v ss v dd 07730-006 figure 6. reference circuit the reference output voltage is 3 v. for applications using the ad7875 or ad7876, a 5 v or 10 v reference may be required. figure 7 shows how to scale the 3 v ref out voltage to provide either a 5 v or 10 v external reference. internal 3v reference ad7870/ad7875/ad7876 ref out 15k? (3.9k ? ) 10k ? (9.1k ? ) v out = 5v (10v) 07730-007 figure 7. generating a 5 v or 10 v reference track-and-hold amplifier the track-and-hold amplifier on the analog input of the ad7870/ad7875/ad7876 allows the adc to accurately convert input frequencies to 12-bit accuracy. the input bandwidth of the track-and-hold amplifier is much greater than the nyquist rate of the adc even when the adc is operated at its maximum throughput rate. the 0.1 db cutoff frequency occurs typically at 500 khz. the track-and-hold amplifier acquires an input signal to 12-bit accuracy in less than 2 s. the overall throughput rate is equal to the conversion time plus the track-and-hold amplifier acquisition time. for a 2.5 mhz input clock the throughput rate is 10 s max. the operation of the track-and-hold is essentially transparent to the user. the track-and-hold amplifier goes from its tracking mode to its hold mode at the start of conversion. if the convst input is used to start conversion then the track to hold transition occurs on the rising edge of convst . if cs starts conversion, this transition occurs on the falling edge of cs . analog input the three parts differ from each other in the analog input voltage range that they can handle. the ad7870 accepts 3 v input signals, the ad7876 accepts a 10 v input range, while the input range for the ad7875 is 0 v to +5 v. figure 8 shows the ad7870 analog input. the analog input range is 3 v into an input resistance of typically 15 k. the designed code transitions occur midway between successive integer lsb values (that is, 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fsC3/2 lsbs). the output code is twos complement binary with 1 lsb = fs/4096 = 6 v/4096 = 1.46 mv. the ideal input/output transfer function is shown in figure 11 . ad7870 track-and-hold amplifier to internal 3v reference r r to internal comparator 07730-008 figure 8. ad7970 analog input the ad7876 analog input structure is shown in figure 9 . the analog input range is 10 v into an input resistance of typically 33 k. as before, the designed code transitions occur midway between successive integer lsb values. the output code is twos complement with 1 lsb = fs/4096 = 20 v/4096 = 4.88 mv. the ideal input/output transfer function is shown in figure 11 .
ad7870/ad7875/ad7876 rev. c | page 12 of 2 8 ad7876 track-and-hold amplifier to internal reference 2.1r 7r v in ref out agnd to internal comparator 07730-009 3r to internal agnd figure 9. ad7876 analog input figure 10 shows the analog input for the ad7875. the input range is 0 v to +5 v into an input resistance of typically 25 k. once again, the designed code transitions occur midway between successive integer lsb values. the output code is straight binary with 1 lsb = fs/4096 = 5 v/4096 = 1.22 mv. the ideal input/output transfer function is shown in figure 12 . ad7875 track-and-hold amplifier to internal agnd 3r 2r v in agnd to internal comparator 07730-010 figure 10. ad7875 analog input 011?111 output code ad7870 (ad7876) 011?110 100?001 100?000 0v v in ? input voltage 000?010 000?001 000?000 111?111 111?110 ?fs 2 +fs ? 1lsb 2 fs 1lsb = fs = 6v (20v) 4096 07730-011 figure 11. ad7870/ad7876 transfer function output code 000?011 000?010 000?001 000?000 v in ? input voltage 111?101 111?100 111?111 111?110 fs 1lsb = fs = 5v +fs ? 1lsb 0v 4096 07730-012 figure 12. ad7875 transfer function offset and full-scale adjustment ad7870 in most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. offset error can always be eliminated in the analog domain by ac coupling. full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the adc. some applications will require that the input signal span the full analog input dynamic range. in such applications, offset and full-scale error have to be adjusted to zero. where adjustment is required, offset error must be adjusted before full-scale error. this is achieved by trimming the offset of the op amp driving the analog input of the ad7870 while the input voltage is 1/2 lsb below ground. the trim procedure is as follows: apply a voltage of ?0.73 mv(?1/2 lsb) at v 1 in figure 13 and adjust the op amp offset voltage until the adc output code flickers between 1111 1111 1111 and 0000 0000 0000. gain error can be adjusted at either the first code transition (adc negative full-scale) or the last code transition (adc positive full scale). the trim procedures for both cases are as follows (see figure 13 ).
ad7870/ad7875/ad7876 rev. c | page 13 of 28 r1 10k? r2 500? r3 10k? agnd v in r5 10k ? r4 10k ? ad7870/ ad7875/ ad7876 1 1 additional pins omitted for clarity. v 1 07730-013 positive full-scale adjust apply a voltage of 9.9927 v (fs/2 ? 3/2 lsbs) at v 1 . adjust r2 until the adc output code flickers between 0111 1111 1110 and 0111 1111 1111. negative full-scale adjust apply a voltage of ?9.9976 v (fs/2 + 1/2 lsb) at v 1 and adjust r2 until the adc output code flickers between 1000 0000 0000 and 1000 0000 0001. offset and full-scale adustment ad7875 figure 13. offset and fu ll-scale adjust circuit similar to the ad7870, most of the dsp applications in which the ad7875 is used do not require offset and full-scale adjustment. for applications that do require adjustment, offset error must be adjusted before full-scale (gain) error. this is achieved by applying an input voltage of 0.61 mv (1/2 lsb) to v 1 in figure 13 and adjusting the op amp offset voltage until the adc output code flickers between 0000 0000 0000 and 0000 0000 0001. for full-scale adjustment, apply an input voltage of 4.9982 v (fs ? 3/2 lsbs) to v 1 and adjust r2 until the adc output code flickers between 1111 1111 1110 and 1111 1111 1111. positive full-scale adjust apply a voltage of 2.9978 v (fs/2 ? 3/2 lsbs) at v 1 . adjust r2 until the adc output code flickers between 0111 1111 1110 and 0111 1111 1111. negative full-scale adjust apply a voltage of ?2.9993 v (?fs/2 + 1/2 lsb) at v 1 and adjust r2 until the adc output code flickers between 1000 0000 0000 and 1000 0000 0001. offset and full-scale adustment ad7876 the offset and full-scale adjustment for the ad7876 is similar to that just outlined for the ad7870. the trim procedure, for those applications that do require adjustment, is as follows: apply a voltage of ?2.44 mv (?1/2 lsb) at v 1 and adjust the op amp offset voltage until the adc output code flickers between 1111 1111 1111 and 0000 0000 0000. full-scale error can be adjusted at either the first code transition (adc negative full scale) or the last code transition (adc positive full scale). the trim procedure for both case is as described in the following sections (see figure 13 ).
ad7870/ad7875/ad7876 rev. c | page 14 of 28 timing and control the ad7870/ad7875/ad7876 is capable of two basic operat- ing modes. in the first mode (mode 1), the convst line is used to start conversion and drive the track-and-hold into its hold mode. at the end of conversion, the track-and-hold returns to its tracking mode. it is intended principally for digital signal processing and other applications where precise sampling in time is required. in these applications, it is important that the signal sampling occur at exactly equal intervals to minimize errors due to sampling uncertainty or jitter. for these cases, the convst line is driven by a timer or some precise clock source. the second mode is achieved by hardwiring the convst line low. this mode (mode 2) is intended for use in systems where the microprocessor has total control of the adc, both initiating the conversion and reading the data. cs starts conversion and the microprocessor is normally driven into a wait state for the duration of conversion by busy / int . data output formats in addition to the two operating modes, the ad7870/ad7875/ ad7876 also offers a choice of three data output formats, one serial and two parallel. the parallel data formats are a single, 12-bit parallel word for 16-bit data buses and a two-byte format for 8-bit data buses. the data format is controlled by the 12/ 8 / clk input. a logic high on this pin selects the 12-bit parallel output format only. a logic low or ?5 v applied to this pin allows the user access to either serial or byte formatted data. three of the pins previously assigned to the four msbs in parallel form are now used for serial communications while the fourth pin becomes a control input for the byte-formatted data. the three possible data output formats can be selected in either of the modes of operation. parallel output format the two parallel formats available on the part are a 12-bit wide data word and a two-byte data word. in the first format, all 12 bits of data are available at the same time on db11 (msb) through db0 (lsb). in the second, two reads are required to access the data. when this data format is selected, the db11/ hben pin assumes the hben function. hben selects which byte of data is to be read from the adc. when hben is low, the lower eight bits of data are placed on the data bus during a read operation; with hben high, the upper four bits of the 12- bit word are placed on the data bus. these four bits are right justified and thereby occupy the lower nibble of data while the upper nibble contains four zeros. serial output format serial data is available on the ad7870/ad7875/ad7876 when the 12/ 8 /clk input is at 0 v or ?5 v and in this case the db10/ sstrb , db9/sclk and db8/sdata pins assume their serial functions. serial data is available during conversion with a word length of 16 bits; four leading zeros, followed by the 12-bit conversion result starting with the msb. the data is synchro- nized to the serial clock output (sclk) and framed by the serial strobe ( sstrb ). data is clocked out on a low to high transition of the serial clock and is valid on the falling edge of this clock while the sstrb output is low. sstrb goes low within three clock cycles after convst , and the first serial data bit (the first leading zero) is valid on the first falling edge of sclk. all three serial lines are open-drain outputs and require external pull-up resistors. the serial clock out is derived from the adc clock source, which may be internal or external. normally, sclk is required during the serial transmission only. in these cases, it can be shut down at the end of conversion to allow multiple adcs to share a common serial bus. however, some serial systems (such as the tms32020) require a serial clock that runs continuously. both options are available on the ad7870/ad7875/ad7876 using the 12/ 8 /clk input. with this input at ?5 v, the serial clock (sclk) runs continuously; when 12/ 8 /clk is at 0 v, sclk is turned off at the end of transmission. mode 1 interface conversion is initiated by a low going pulse on the convst input. the rising edge of this convst pulse starts conversion and drives the track-and-hold amplifier into its hold mode (ad7870/ad7875/ad7876). the falling edge of the convst pulse starts conversion and drives the track-and-hold amplifier into its hold mode (ad7870a). conversion is not initiated if the cs is low. the busy / int status output assumes its int function in this mode. int is normally high and goes low at the end of conversion. this int line can be used to interrupt the microprocessor. a read operation to the adc accesses the data and the int line is reset high on the falling edge of cs and rd . the convst input must be high when cs and rd are brought low for the adc to operate correctly in this mode. the cs or rd input should not be hardwired low in this mode. data cannot be read from the part during conversion because the on- chip latches are disabled when conversion is in progress. in applications where precise sampling is not critical, the convst pulse can be generated from a microprocessor wr line or-gated with a decoded address. in some applications, depending on power supply turn-on time, the ad7870/ad7875/ad7876 may perform a conversion on power-up. in this case, the int line powers-up low and a dummy read to the ad7870/ad7875/ad7876 is required to reset the int line before starting conversion. figure 18 shows the mode 1 timing diagram for a 12-bit parallel data output format (12/ 8 /clk = +5 v). a read to the adc at the end of conversion accesses all 12 bits of data at the same time. serial data is not available for this data output format.
ad7870/ad7875/ad7876 rev. c | page 15 of 28 convst track-and-hold goes into hold track-and-hold returns to track and acquisition time begins three-state valid data db11 to db0 cs rd int data t 2 t 1 t convert t 5 t 4 t 7 t 4 t 3 07730-014 figure 14. mode 1 timing diagram, 12-bit parallel read convst cs rd int sstrb 2 data sclk 3 track-and-hold returns to track and acquisition time begins track-and-hold goes into hold three-state leading zeros valid data db7 to db0 valid data db11 to db8 hben 1 t 1 sdata 2 1 times t 2 , t 3 , t 4 , t 8 , and t 9 are the same for a high byte read as for a low byte read. 2 external 4.7k ? pull-up resistor. 3 external 2k ? pull-up resistor; continuous sclk (dashed line) when 12/8/clk = ?5v; noncontinuous when 12/8/clk = 0v. db11 db10 serial data db0 t 8 t 2 t 4 t 3 t 9 t 7 t 5 t convert t 6 t 11 t 10 t 12 t 13 07730-015 t 14 figure 15. mode 1 timing diagram, byte or serial read the mode 1 timing diagram for byte and serial data is shown in figure 15 . int goes low at the end of conversion and is reset high by the first falling edge of cs and rd . this first read at the end of conversion can either access the low byte or high byte of data depending on the status of hben ( shows low byte only for example). the diagram shows both a nonconti- nuously and a continuously running clock (dashed line). figure 15 mode 2 interface the second interface mode is achieved by hard wiring convst low and conversion is initiated by taking cs low while hben is low. the track-and-hold amplifier goes into the hold mode on the falling edge of cs . in this mode, the busy / int pin assumes its busy function. busy goes low at the start of conversion, stays low during the conversion and returns high when the conversion is complete. it is normally used in parallel interfaces to drive the microprocessor into a wait state for the duration of conversion. mode 2 is not relevant for the ad7870a device. figure 16 shows the mode 2 timing diagram for the 12-bit parallel data output format (12/ 8 /clk = +5 v). in this case, the adc behaves like slow memory. the major advantage of this interface is that it allows the microprocessor to start conversion, wait and then read data with a single read instruction. the user does not have to worry about servicing interrupts or ensuring that software delays are long enough to avoid reading during conversion.
ad7870/ad7875/ad7876 rev. c | page 16 of 28 cs track-and-hold goes into hold track-and-hold returns to track and acquisition time begins three-state valid data db11 to db0 rd busy data t 15 t 17 t 7 07730-016 t 16 t convert t 18 figure 16. mode 2 timing diagram, 12-bit parallel read cs rd busy sstrb 2 data sclk 3 track-and-hold returns to track and acquisition time begins track-and-hold goes into hold three-state leading zeros valid data db7 to db0 valid data db11 to db8 hben 1 sdata 2 1 times t 15 , t 16 , and t 20 are the same for a high byte read as for a low byte read. 2 external 4.7k ? pull-up resistor. 3 external 2k ? pull-up resistor; continuous sclk (dashed line) when 12/8/clk = ?5v; noncontinuous when 12/8/clk = 0v. db11 db10 serial data db0 t 8 t 2 t 18 t 20 t 7 t 6 t 7 t 6 t 17 t 11 t 10 t 16 t 15 t 19 t convert t 13 t 14 t 12 0 7730-017 figure 17. mode 2 timing diagram, byte or serial read the mode 2 timing diagram for byte and serial data is shown in figure 17 . for a two-byte data read, the lower byte (db0 C db7) has to be accessed first since hben must be low to start conver- sion. the adc behaves like slow memory for this first read, but the second read to access the upper byte of data is a normal read. operation of the serial functions is identical between mode 1 and mode 2. the timing diagram of figure 17 shows both a noncontinuously and a continuously running sclk (dashed line). dynamic specifications the ad7870 and ad7875 are specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as integral and differential nonlinearity. although the ad7876 is not production tested for ac parameters, its dynamic performance is similar to the ad7870 and ad7875. the ac specifications are required for signal processing applications such as speech recognition, spectrum analysis and high speed modems. these applications require information on the adcs effect on the spectral content of the input signal. thus, the parameters for which the ad7870 and ad7875 are specified include snr, harmonic distortion, intermodulation distortion and peak harmonics. these terms are discussed in more detail in the following sections. signal-to-noise ratio (snr) snr is the measured signal-to-noise ratio at the output of the adc. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fs/2) excluding dc. snr is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal-to-noise ratio for a sine wave input is given by snr = (6.02n + 1.76) db (1) where n is the number of bits. thus for an ideal 12-bit converter, snr = 74 db. note that a sine wave signal is of very low distortion to the v in input which is sampled at a 100 khz sampling rate. a fast
ad7870/ad7875/ad7876 rev. c | page 17 of 28 fourier transform (fft) plot is generated from which the snr data can be obtained. figure 18 shows a typical 2048 point fft plot of the ad7870kn/ad7875kn with an input signal of 25 khz and a sampling frequency of 100 khz. the snr obtained from this graph is 72.6 db. it should be noted that the harmonics are taken into account when calculating the snr. 0 ?30 ?60 ?90 ?120 ?140 0 25 50 07730-018 signal amplitude (db) frequency (khz) input frequency = 25khz sample frequency = 100khz snr = 72.6db t a = 25c figure 18. fft plot effective number of bits the formula given in equation 1 relates snr to the number of bits. rewriting the formula, as in equation 2, it is possible to get a measure of performance expressed in effective number of bits (n). 02.6 76.1 ? = (2) the effective number of bits for a device can be calculated directly from its measured snr. figure 19 shows a typical plot of effective number of bits vs. frequency for an ad7870kn/ad7875kn with a sampling frequency of 100 khz. the effective number of bits typically falls between 11.7 and 11.85 corresponding to snr figures of 72.2 and 73.1 db. 12.0 11.5 11.0 10.5 10.0 0 12.5 18.75 6.25 25.0 31.25 37.5 43.75 50.0 07730-019 effective number of bits input frequency (khz) sample frequency = 100khz t a = 25c figure 19. effective number of bits vs. frequency total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad7870/ad7875, thd is defined as 1 2 6 2 5 2 4 2 3 2 2 log20 v vvvvv thd ++++ = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonic. the thd is also derived from the fft plot of the adc output spectrum. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). using the ccif standard, where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. in this case, the input consists of two, equal amplitude, low distortion sine waves. figure 20 shows a typical imd plot for the ad7870/ad7875. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor the peak is a noise peak.
ad7870/ad7875/ad7876 rev. c | page 18 of 28 0 ?30 ?60 ?90 ?120 05 v(i), the estimated code transition point, is derived as follows: 0 07730-020 signal amplitude (db) frequency (khz) input frequencies f1 = 9.05khz f2 = 9.55khz sampling frequency = 100khz t a = 25c imd all terms = 90.06db second order terms = 92.73db third order tersm = 93.45db () () [ ] n icum cosaiv ?= where: a is the peak signal amplitude. n is the number of histogram samples. cum(i) = () = i n nv 0 occurrences. 0.5 ?0.50 0.25 0 ?0.25 0 511 1023 1535 2047 2559 3071 3583 4095 07730-021 ac relative accuracy (lsb) code input frequency = 25khz sample frequency = 100khz t a = 25c figure 20. imd plot ac linearity plot when a sine wave of specified frequency is applied to the v in input of the ad7870/ad7875 and several million samples are taken, a histogram showing the frequency of occurrence of each of the 4096 adc codes can be generated. from this histogram data it is possible to generate an ac integral linearity plot as shown in figure 21 . this shows very good integral linearity performance from the ad7870/ad7875 at an input frequency of 25 khz. the absence of large spikes in the plot shows good differential linearity. simplified versions of the formulae used are outlined below. figure 21. ac inl plot () () () () () i ovfsv oviv iinl ? ? ? ? ? ? ? ? ? ? ? = 4096 where: inl(i) is the integral linearity at code i. v(fs) and v(o) are the estimated full-scale and offset transitions. v(i) is the estimated transition for the i th code.
ad7870/ad7875/ad7876 rev. c | page 19 of 28 microprocessor interface the ad7870/ad7875/ad7876 have a wide variety of interfacing options. they offer two operating modes and three data-output formats. fast data access times allow direct interfacing to most microprocessors including the dsp processors. parallel read interfacing figure 22 , figure 23 , and figure 24 show interfaces to the adsp-2100, tms32010 and the tms32020 dsp processors. the adc is operating in mode 1, parallel read for all three interfaces. an external timer controls conversion start asyn- chronously to the microprocessor. at the end of each conversion the adc busy / int interrupts the microprocessor. the conversion result is read from the adc with the following instruction: adsp-2100: mr0 = dm(adc) tms32010: in d,adc tms32020: in d,adc mr0 = adsp-2100 mr0 register d = data memory address adc = ad7870/ad7875/ad7876 address some applications may require that conversions be initiated by the microprocessor rather than an external timer. one option is to decode the convst signal from the address bus so that a write operation to the adc starts a conversion. data is read at the end of conversion as described earlier. note: a read operation must not be attempted during conversion. dma13 dma0 convst timer cs 5v 12/8/clk busy/int rd db11 db0 1 additional pins omitted for clarity. address bus data bus addr decode en dms irqn dmrd dmd15 dmd0 ad7870/ ad7875/ ad7876 1 adsp-2100 07730-022 figure 22. adsp-2100 parallel interface pa2 pa0 convst timer cs 5v 12/8/clk busy/int rd db11 db0 1 additional pins omitted for clarity. address bus data bus addr decode en men int den d15 d0 ad7870/ ad7875/ ad7876 1 tms32010 07730-023 figure 23. tms32010 parallel interface a15 a0 convst timer cs 5v 12/8/clk busy/int rd db11 db0 address bus data bus addr decode en is intn strb d15 d0 r/w tms32020 07730-024 1 additional pins omitted for clarity. ad7870/ ad7875/ ad7876 1 figure 24. tms32020 parallel interface two-byte read interfacing 68008 interface figure 25 shows an 8-bit bus interface for the mc68008 micro- processor. for this interface, the 12/ 8 /clk input is tied to 0 v and the db11/hben pin is driven from the microprocessor least significant address bit. conversion start control is provided by the microprocessor. in this interface example, a move instruc- tion from the adc address both starts a conversion and reads the conversion result. movew adc,do adc = ad7870/ad7875/ad7876 address d0 = 68008 d0 register
ad7870/ad7875/ad7876 rev. c | page 20 of 2 8 this is a two-byte read instruction. during the first read operation busy , in conjunction with cs , forces the micro- processor to wait for the adc conversion. at the end of conversion the adc low byte (db7 C db0) is loaded into d15 C d8 of the d0 register and the adc high byte (db15 C db7) is loaded into bits d7 C d0 of the d0 register. the following rotate instruction to the d0 register swaps the high and low bytes to the correct format. r0l = 8, d0. note that while executing the two-byte read instruction above, wait states are inserted during the first read operation only and not for the second. a15 a0 convst cs hben a0 12/8/clk busy/int rd db7 c r 2 db0 address bus data bus addr decode en dtack as strb d15 d0 r/w 07730-025 1 additional pins omitted for clarity. 2 resistor and capacitor required to guarantee t 15 . ad7870/ ad7875/ ad7876 1 mc68008 figure 25. mc68008 byte interface serial interfacing figure 26 , figure 27 , figure 28 , and figure 29 show the ad7870/ad7875/ad7876 configured for serial interfacing. in all four interfaces, the adc is configured for mode 1 operation. the interfaces show a timer driving the convst input, but this could be generated from a decoded address if required. the sclk, sdat and sstrb are open-drain outputs. if these are required to drive capacitive loads in excess 35 pf, buffering is recommended. dsp56000 serial interface figure 26 shows a serial interface between the ad7870/ad7875/ ad7876, and the dsp56000. the interface arrangement is two-wire with the adc configured for noncontinuous clock operation (12/ 8 /clk = 0 v). the dsp56000 is configured for normal mode asynchronous operation with gated clock. it is also set up for a 16-bit word with sck and sc1 as inputs and the fsl control bit set to a 0. in this configuration, the dsp56000 assumes valid data on the first falling edge of sck. since the adc provides valid data on this first edge, there is no need for a strobe or framing pulse for the data. sclk and sdata are gated off when the adc is not performing a conversion. during conversion, data is valid on the sdata output of the adc and is clocked into the receive data shift register of the dsp56000. when this register has received 16 bits of data, it generates an internal interrupt on the dsp56000 to read the data from the register. convst 12/8/clk sclk 2k? 5v 4.7k ? sdata sck srd dsp56000 07730-026 timer 1 additional pins omitted for clarity. ad7870/ ad7875/ ad7876 1 figure 26. dsp56000 serial interface the dsp56000 and ad7870/ad7875/ad7876 can also be configured for continuous clock operation (12/ 8 /clk = ?5 v). in this case, a strobe pulse is required by the dsp56000 to indicate when data is valid. the sstrb output of the adc is inverted and applied to the sc1 input of the dsp56000 to provide this strobe pulse. all other conditions and connections are the same as for gated clock operation. nec7720/77230 serial interface a serial interface between the ad7870/ad7875/ad7876 and the nec7720 is shown in figure 27 . in the interface shown, the adc is configured for continuous clock operation. this can be changed to a noncontinuous clock by simply tying the 12/ 8 /clk input of the adc to 0 v with all other connections remaining the same. the nec7720 expects valid data on the rising edge of its sck input and therefore an inverter is required on the sclk output of the adc. the nec7720 is configured for a 16-bit data word. once the 16 bits of data have been received by the si register of the nec7720, an internal interrupt is generated to read the contents of the si register. the nec77230 interface is similar to that just outlined for the nec7720. however, the clock input of the nec77230 is siclk. additionally, no inverter is required between the adc sclk output and this siclk input since the nec77230 assumes data is valid on the falling edge of siclk. convst 12/8/clk 2k? +5v ?5v 4.7k ? 4.7k ? sclk sien si sclk sstrb sdata pd7720 07730-027 timer 1 additional pins omitted for clarity. ad7870/ ad7875/ ad7876 1 figure 27. nec7720 serial interface
ad7870/ad7875/ad7876 rev. c | page 21 of 2 8 convst 12/8/clk 2k? +5v ?5v 4.7k ? 4.7k ? clkr fsr dr sclk sstrb sdata adsp-2101/ adsp-2102 07730-029 timer 1 additional pins omitted for clarity. ad7870/ ad7875/ ad7876 1 tms32020 serial interface figure 28 shows a serial interface between the ad7870/ ad7875/ad7876 and the tms32020. the ad7870/ad7875/ ad7876 is configured for continuous clock operation. note that the adc will not interface correctly to the tms32020 if the adc is configured for a noncontinuous clock. data is clocked into the data receive register (drr) of the tms32020 during conversion. as with the previous interfaces, when a 16-bit word is received by the tms32020 it generates an internal interrupt to read the data from the drr. convst 12/8/clk 2k? 5v ?5v 4.7k ? 4.7k ? clkr fsr dr sclk sstrb sdata tms32020 07730-028 timer 1 additional pins omitted for clarity. ad7870/ ad7875/ ad7876 1 figure 29. adsp-2101/adsp-2102 serial interface standalone operation the ad7870/ad7875/ad7876 can be used in its mode 2, parallel interface mode for standalone operation. in this case, conversion is initiated with a pulse to the adc cs input. this pulse must be longer than the conversion time of the adc. the busy output is used to drive the rd input. data is latched from the adc db0Cdb11 outputs to an external latch on the rising edge of busy . cs t cs 1 1 t cs > t 16 + t convert . 2 additional pins omitted for clarity. busy db11 rd db0 en latch 07730-030 ad7870/ ad7875/ ad7876 2 figure 28. tms32020 serial interface adsp-2101/adsp-2102 serial interface figure 29 shows a serial interface between the ad7870/ ad7875/ad7876 and the adsp-2101/adsp-2102. the adc is configured for continuous clock operation. data is clocked into the serial port register of the adsp-2101/adsp-2102 during conversion. as with the previous interfaces, when a 16- bit data word is received by the adsp-2101/adsp-2102 an internal microprocessor interrupt is generated and the data is read from the serial port register. figure 30. stand-alone operation
ad7870/ad7875/ad7876 rev. c | page 22 of 2 8 applications information good printed circuit board (pcb) layout is as important as the overall circuit design itself in achieving high speed analog- to-digital performance. the designer has to be conscious of noise both in the adc itself and in the preceding analog circuitry. switching mode power supplies are not recommended because the switching spikes feed through to the comparator causing noisy code transitions. other causes of concern are ground loops and digital feedthrough from microprocessors. these are factors which influence any adc, and a proper pcb layout which minimizes these effects is essential for best performance. layout hints ensure that the layout for the printed circuit board has the digital and analog signal lines separated as much as possible. take care not to run any digital track alongside an analog signal track. guard (screen) the analog input with agnd. establish a single point analog ground (star ground) separate from the logic system ground at the agnd pin or as close as possible to the adc. connect all other grounds and the ad7870/ad7875/ad7876 dgnd to this single analog ground point. do not connect any other digital grounds to this analog ground point. low impedance analog and digital power supply common returns are essential to low noise operation of the adc, so make the foil width for these tracks as wide as possible. the use of ground planes minimizes impedance paths and also guards the analog circuitry from digital noise. the circuit layout has both analog and digital ground planes which are kept separated and only joined together at the ad7870/ ad7875/ad7876 agnd pin. noise keep the input signal leads to v in and signal return leads from agnd as short as possible to minimize input noise coupling. in applications where this is not possible, use a shielded cable between the source and the adc. reduce the ground circuit impedance as much as possible since any potential difference in grounds between the signal source and the adc appears as an error voltage in series with the input signal.
ad7870/ad7875/ad7876 rev. c | page 23 of 2 8 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 071006-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) bsc 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 31. 24-lead plastic dual in-line package [pdip] narrow body (n-24-1) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 24 11 2 13 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) pin 1 100808-a figure 32. 24-lead ceramic dual in-line package [cerdip] narrow body (q-24-1) dimensions shown in inches and (millimeters)
ad7870/ad7875/ad7876 rev. c | page 24 of 2 8 compliant to jedec standards mo-047-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 4 5 26 25 11 12 19 18 top view (pins down) sq 0.456 (11.582) 0.450 (11.430) 0.050 (1.27) bsc 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32) sq 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.120 (3.04) 0.090 (2.29) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.180 (4.57) 0.165 (4.19) bottom view (pins up) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier 042508-a figure 33. 28-lead plastic leaded chip carrier [plcc] (p-28) dimensions shown in inches and (millimeters) compliant to jedec standards ms-013-ad controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 24 13 12 1 1.27 (0.0500) bsc 060706-a figure 34. 24-lead standard small outline package [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches)
ad7870/ad7875/ad7876 rev. c | page 25 of 2 8 ordering guide table 7. model temperature range v in voltage range (v) snr (dbs) integral nonlinearity (lsb) package description package option ad7870jn 0c to +70c 3 70 min 1/2 typ 24-lead pdip n-24-1 ad7870jnz 1 0c to +70c 3 70 min 1/2 typ 24-lead pdip n-24-1 ad7870kn 0c to +70c 3 70 min 1 max 24-lead pdip n-24-1 ad7870knz 1 0c to +70c 3 70 min 1 max 24-lead pdip n-24-1 ad7870ln 0c to +70c 3 72 min 1/2 max 24-lead pdip n-24-1 ad7870lnz 1 0c to +70c 3 72 min 1/2 max 24-lead pdip n-24-1 ad7870jp 0c to +70c 3 70 min 1/2 typ 28-lead plcc p-28 ad7870jp-reel 0c to +70c 3 70 min 1/2 typ 28-lead plcc p-28 ad7870jpz 1 0c to +70c 3 70 min 1/2 typ 28-lead plcc p-28 ad7870jpz-reel 1 0c to +70c 3 70 min 1/2 typ 28-lead plcc p-28 ad7870kp 0c to +70c 3 70 min 1 max 28-lead plcc p-28 ad7870kp-reel 0c to +70c 3 70 min 1 max 28-lead plcc p-28 ad7870kpz 1 0c to +70c 3 70 min 1 max 28-lead plcc p-28 ad7870kpz-reel 1 0c to +70c 3 70 min 1 max 28-lead plcc p-28 ad7870lp 0c to +70c 3 72 min 1/2 max 28-lead plcc p-28 ad7870lp-reel 0c to +70c 3 72 min 1/2 max 28-lead plcc p-28 ad7870lpz 1 0c to +70c 3 72 min 1/2 max 28-lead plcc p-28 ad7870aq ?25c to +85c 3 70 min 1/2 typ 24-lead cerdip q-24-1 ad7870bq ?25c to +85c 3 70 min 1 max 24-lead cerdip q-24-1 ad7870cq ?25c to +85c 3 72 min 1/2 max 24-lead cerdip q-24-1 ad7870tq ?55c to +125c 3 70 min 1 max 24-lead cerdip q-24-1 ad7875kn 0c to +70c 0 to +5 70 min 1 max 24-lead pdip n-24-1 ad7875knz 1 0c to +70c 0 to +5 70 min 1 max 24-lead pdip n-24-1 ad7875ln 0c to +70c 0 to +5 72 min 1/2 max 24-lead pdip n-24-1 ad7875lnz 1 0c to +70c 0 to +5 72 min 1/2 max 24-lead pdip n-24-1 ad7875kp 0c to +70c 0 to +5 70 min 1 max 28-lead plcc p-28 ad7875kpz 1 0c to +70c 0 to +5 70 min 1 max 28-lead plcc p-28 ad7875kpz-reel 1 0c to +70c 0 to +5 70 min 1 max 28-lead plcc p-28 ad7875lp-reel 0c to +70c 0 to +5 72 min 1/2 max 28-lead plcc p-28 ad7875lpz 1 0c to +70c 0 to +5 72 min 1/2 max 28-lead plcc p-28 ad7875lpz-reel 1 0c to +70c 0 to +5 72 min 1/2 max 28-lead plcc p-28 ad7875bq ?40c to +85c 0 to +5 70 min 1 max 24-lead cerdip q-24-1 ad7875cq ?40c to +85c 0 to +5 72 min 1/2 max 24-lead cerdip q-24-1 ad7875tq ?55c to +125c 0 to +5 70 min 1 max 24-lead cerdip q-24-1 ad7876bn ?40c to +85c 10 1 max 24-lead pdip n-24-1 ad7876bnz 1 ?40c to +85c 10 1 max 24-lead pdip n-24-1 ad7876cn ?40c to +85c 10 1/2 max 24-lead pdip n-24-1 ad7876cnz 1 ?40c to +85c 10 1/2 max 24-lead pdip n-24-1 ad7876br ?40c to +85c 10 1 max 24-lead soic_w rw-24 ad7876br-reel ?40c to +85c 10 1 max 24-lead soic_w rw-24 ad7876br-reel7 ?40c to +85c 10 1 max 24-lead soic_w rw-24 ad7876brz 1 ?40c to +85c 10 1 max 24-lead soic_w rw-24 ad7876brz-reel 1 ?40c to +85c 10 1 max 24-lead soic_w rw-24 ad7876brz-reel7 1 ?40c to +85c 10 1 max 24-lead soic_w rw-24 ad7876cr ?40c to +85c 10 1/2 max 24-lead soic_w rw-24 ad7876cr-reel ?40c to +85c 10 1/2 max 24-lead soic_w rw-24 ad7876crz 1 ?40c to +85c 10 1/2 max 24-lead soic_w rw-24 ad7876bq ?40c to +85c 10 1 max 24-lead cerdip q-24-1 ad7876tq ?55c to +125c 10 1 max 24-lead cerdip q-24-1 1 z = rohs compliant part.
ad7870/ad7875/ad7876 rev. c | page 26 of 2 8 notes
ad7870/ad7875/ad7876 rev. c | page 27 of 2 8 notes
ad7870/ad7875/ad7876 rev. c | page 28 of 28 notes ?1997C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07730-0-2/09(c)

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